1. Technical Field
The present invention relates to a semiconductor memory device, more particularly, the present invention relates to a flash memory device and a system including the same.
2. Description of Related Art
A flow chart for describing a programming method of a conventional nonvolatile memory device is depicted in FIG. 1. FIG. 2 shows threshold voltage distributions of a nonvolatile memory device which stores 1-bit data and 2-bit data per cell. A typical programming method of a nonvolatile memory device will be described below with reference to FIG. 1 and FIG. 2.
Once a programming operation is initiated, data to-be-programmed is loaded in the nonvolatile memory device in S1. On completion of loading of data to-be-programmed, the loaded data is programmed in a memory cell array of the nonvolatile memory device in a well-known programming method, in S2. In S3, a verification reading operation is performed to determine whether the programmed memory cells have the required threshold voltage. The data read in accordance with the verification reading operation is temporarily stored in a register. In S4, the data stored in the register is sequentially selected in a predetermined or reference unit, and the selected data is mounted in an internal data bus. This operation is referred to as a “column scan operation”. In S5, it is determined whether the data bits in the predetermined or reference unit that are mounted in the internal data bus have a program fail data value. That is to say, it is determined whether the programming operations are successfully carried out or not. In case at least one of the data bits of the predetermined or reference unit that are mounted on the internal data bus have a program fail data value, it is determined, in S6, whether the present program loop is a maximum program loop. If the present program loop is not the maximum program loop, the process is moved back to S2. If the present program loop is the maximum program loop, the programming operation is processed as a program fail and the programming process is ended. Going back to S5, if the data bits of the predetermined or reference unit mounted on the internal data bus all have the program pass data value, in S8, the programming operation is processed as a program pass and the program process is ended.
As can be seen from the above description, the programming operation is performed by a plurality of program loops, each of which includes a program interval corresponding to S2 and a program verification interval corresponding to S3 to S5. The program loops are performed repeatedly for the maximum program loop number until the selected memory cells are programmed entirely. As is well known in the art, a program voltage will be incremented for a predetermined or reference increment when the program loops are repeated. In other words, the programming operation will be performed using the Incremental Step Pulse Program (ISPP) scheme. Even in case a portion (e.g. one data bit) of the data bits to-be-programmed is not programmed, the program loops will be repeated up to a maximum program loop number. Since a program voltage increases as the program loops number increases, memory cells supplied with high voltages (e.g. program voltage, pass voltage) may be overly programmed. In other words, a program disturbance and/or a pass voltage disturbance may occur. This may cause widening of a threshold voltage distribution and/or transfer of the threshold voltage distribution as is shown in FIG. 2. Even in case a programming operation is determined as a program pass, over-programming of the memory cells may cause read error due to the widening of a threshold voltage distribution and/or the transfer of the threshold voltage distribution. As a result, there may occur a device fail indicating that a nonvolatile memory device cannot be used.